A fully-buffered dual in-line memory module (FB-DIMM) may utilize an advanced memory buffer (AMB), which is typically disposed on one side of the module. An AMB may have three ports of communication. These ports include high speed serial lanes, which communicate to and from a host mother board chipset via an edge connector and possibly other FB-DIMMs, and an SMBus that provides slow speed two wire serial access for writing and reading configuration and status registers. A high speed parallel interface is also provided that supports bidirectional communication with all DRAMs on the DIMM. This FB-DIMM architecture represents the next generation of DIMMs that can increase the density and bandwidth of a single DIMM and support greater mother board expansion to include more DIMMs.
During normal modes of operation, an FB-DIMM provides no direct access from the edge connector to the DRAMs on the module. Instead, the AMB is responsible for communicating with the edge connector and generating and receiving all signals to and from the DRAMs. The AMB is also responsible for generating the correct timing of signals to and from the DRAMs. Typical AMBs may operate at a data rate from 3.2 Gb/s to 4.8 Gb/s and support as few as nine and as many as 36 DRAMs of different type, while also supporting ×4 and ×8 data width modes. In order to support this wide range in operating conditions, an AMB includes internal registers that are programmable with configuration data. These internal registers may be accessible by either the SMBus or in-band commands on the high speed serial lanes.
As will be understood by those skilled in the art, an AMB may experience reduced timing margins when the FB-DIMM is running at its maximum speed (e.g., the 4.8 Gb/s rate translates to a 400 MHz DRAM clock or an 800 Mb/s DDR data interface). At this maximum speed, the clock period is nominally 2.5 ns, and the half period or data eye maximum is 1.25 ns. Generating signals that meet these reduced timing margins is difficult because of the presence of timing skew between data, address, command, strobe and clock signals generated to and from the DRAMs. This timing skew is at least partially caused by the physical line length differences between the AMB and the closest and farthest DRAMs on both sides of the DIMM.
Referring now to FIG. 1, an integrated circuit system 100 is illustrated as including a dual in-line memory module (DIMM) 30 that communicates with a host processor 10 via a high speed serial bus (HSS_BUS) and an SMBus that provides two-wire serial access for writing and reading configuration and status registers within a memory buffer 20 on the DIMM 30. The memory buffer 20 and a plurality of DRAMs 22_1 to 22_8 are disposed on the DIMM 30. The DRAMs 22_1 to 22_8 are coupled to the memory buffer 20 by a high speed parallel interface. These DRAMs 22_1 to 22_8 are illustrated as being disposed on one side of a printed circuit board having an edge connector 32 that may be configured to be received within a dual in-line connector mounted on a mother board (not shown). Additional DRAMs may also be provided on both sides of the DIMM 30.
As illustrated by FIG. 2A, the memory buffer 20 includes a buffer control circuit 24 and a DRAM interface circuit 26. The buffer control circuit 24 includes a multi-lane I/O interface, which supports coupling to the high speed serial bus (HSS_BUS). This multi-lane I/O interface may include fully-buffered I/O drivers and phase-locked loop (PLL) integrated circuits that are configured to receive a reference clock signal (REFCLK). The buffer control circuit 24 also includes user accessible configuration and status registers (not shown). An exemplary DRAM interface circuit 26, which receives control signals from the configuration and status registers, is more fully illustrated by FIG. 2B. This DRAM interface circuit 26 includes a plurality of driver circuits that service a front side of the DIMM 30 and a plurality of driver circuits that service a back side of the DIMM 30. With respect to the front side (side A) of the DIMM 30, the driver circuits include a first clock driver circuit 28-1, a first address driver circuit 28-2, first command driver circuits 28-3 and 28-4 and a front on-die termination (ODTA) driver circuit 28-5. With respect to the back side (side B) of the DIMM 30, the driver circuits include a second clock driver circuit 28-6, a second address driver circuit 28-7, second command driver circuits 28-8 and 28-9 and a back on-die termination (ODTB) driver circuit 28-10. A ×18 data and strobe driver circuit 28-11 is also provided, which is responsive to eighteen multi-bit data skew control signals dout_ctl[8:0] and eighteen multi-bit strobe skew control signals dqs_ctl [8:0]. These skew control signals may be stored within the user accessible configuration registers. These multi-bit skew control signals may support a skew resolution of 6.5 ps in 384 steps, which covers one full period of an interface clock signal operating at 400 MHz.
The first clock driver circuit 28-1 is a ×2 circuit (i.e., includes two copies of the elements illustrated within the dotted box), with each circuit including a phase interpolator (PI), a flip-flop having complementary outputs and a pair of output buffers/drivers that generate a corresponding pair of true and complementary clock signals CLK and CLK#. FIG. 2C illustrates an exemplary output buffer/driver 32 that can be used in the first clock driver circuit 28-1. This output buffer/driver 32 may include a pre-driver stage and an output driver stage connected in series, with the pre-driver stage being responsive to the slew rate control signal (slew_ctl) and the output driver stage being responsive to the output impedance control signal (imp_ctl). In particular, the pre-driver stage may be configured so that the slew rate of its output can be set in response to the slew rate control signal (slew_ctl) and the pull-up and pull-down impedances of the output driver stage can be set in response to the output impedance control signal (imp_ctl). These control signals (slew_ctl and imp_ctl) provide the same degree of independent control as the various skew control signals described herein. The output buffer/driver 32 may be of conventional design and need not be described further herein.
Each phase interpolator (PI) in the first clock driver circuit 28-1 is configured to receive a plurality of timing signals. As illustrated, these timing signals include three phases of an interface clock signal (e.g., 400 MHz clock signal) generated by a phase-locked loop (PLL) integrated circuit (not shown). The three phases are separated by 60° relative to each other. From these three phases, each phase interpolator may generate three additional phases by inverting each of the illustrated timing signals. In this manner, a total of six phases may be generated that are separated by 60°. In alternative embodiments, all six phases may be generated by the PLL integrated circuit and provided as timing signals to the illustrated phase interpolators (PI).
Each phase interpolator is also responsive to a respective multi-bit clock skew control signal (clk_ctl), which controls the phase of the periodic signal at the output of the phase interpolator. This output is provided as a clock signal to a corresponding flip-flop. In this manner, the values of the clock skew control signals (clk_ctl) operates to set the phases of the complementary outputs of the flip-flops and the phases of the true and complementary clock signals (CLK[0], CLK[0]#) and (CLK[2], CLK[2]#).
The first address driver circuit 28-2 is a ×19 circuit (i.e., includes nineteen copies of the elements illustrated within the dotted box), with each circuit including a flip-flop having a true output and an output buffer/driver that generates a corresponding bit of an address signal (column and row address (A) and bank address (BA)). The output buffer/driver may be as illustrated by FIG. 2C and described hereinabove. Unlike the first clock driver circuit 28-1, only one phase interpolator (PI) is used in the first address driver circuit 28-2. The phase interpolator, which is responsive to the plurality of timing signals and the address skew control signal (addr_ctl), sets the skew associated with all nineteen bits of the address signals (A[15:0]A, BA[2:0]A).
The command driver circuit 28-3 is a ×3 circuit (i.e., includes three copies of the elements illustrated within the dotted box), with each circuit including a flip-flop having a true output and an output buffer/driver that generates a corresponding command. The three flip-flops are configured to receive a front side row address strobe input signal (ras), a front side column address strobe input signal (cas) and a front side write enable input signal (we), respectively. The generated commands include an active low row address strobe signal RAS#A, an active low column address strobe signal CAS#A and an active low write enable signal WE#A, which are provided to the front side of the DIMM 30. The phase interpolator, which is responsive to the plurality of timing signals and a command skew control signal (rascaswe_ctl), sets the skew associated with all three commands (RAS#A, CAS#A and WE#A).
The command driver circuit 28-4 is a ×4 circuit (i.e., includes four copies of the elements illustrated within the dotted box), with each circuit including a flip-flop having a true output and an output buffer/driver that generates a corresponding command. The four flip-flops are configured to receive a pair of chip select signals and a pair of clock enable signals (cs and cke, which correspond to cs[1:0]#A and cke[1:0]A). The phase interpolator, which is responsive to the plurality of timing signals and a command skew control signal (cscke_ctl), sets the skew associated with all four commands (CS[1:0]#A and CKE[1:0]A). The skews of CS[0]#A and CKE[0]A may be set independently of CS[1]#A and CKE[1]A.
The front on-die termination (ODTA) driver circuit 28-5 includes a flip-flop having a true output and an output buffer/driver that generates a corresponding on-die termination signal (ODTA) for the front side of the DIMM 30. The flip-flop is configured to receive an on-die termination signal (odt) for the front side. The phase interpolator, which is responsive to the plurality of timing signals and an ODT skew control signal (odt_ctl), sets the skew associated the front on-die termination signal (ODTA).
The second clock driver circuit 28-6 is a ×2 circuit (i.e., includes two copies of the elements illustrated within the dotted box), with each circuit including a phase interpolator (PI), a flip-flop having complementary outputs and a pair of output buffers/drivers that generate a corresponding pair of true and complementary clock signals CLK and CLK#. FIG. 2C illustrates an exemplary output buffer/driver circuit 32 that can be used in the second clock driver circuit 28-6. Each phase interpolator (PI) in the second clock driver circuit 28-6 is configured to receive the plurality of timing signals. Each phase interpolator is also responsive to a respective multi-bit clock skew control signal (clk_ctl) for the back side of the DIMM 30. The values of the two clock skew control signals (clk_ctl) for the back side operate to set the phases of the complementary outputs of the flip-flops and the phases of the true and complementary clock signals (CLK[1], CLK[1]#) and (CLK[3], CLK[3]#).
The second address driver circuit 28-7 is a ×19 circuit (i.e., includes nineteen copies of the elements illustrated within the dotted box), with each circuit including a flip-flop having a true output and an output buffer/driver that generates a corresponding bit of an address signal (column and row address (A) and bank address (BA)) for the back side. The output buffer/driver may be as illustrated by FIG. 2C and described hereinabove. Unlike the first clock driver circuit 28-1, only one phase interpolator (PI) is used in the second address driver circuit 28-7. Thus, the fanout at the output of the phase interpolator is nineteen. The phase interpolator, which is responsive to the plurality of timing signals and the address skew control signal (addr_ctl) for the back side, sets the skew associated with all nineteen bits of the address signals (A[15:0]B, BA[2:0]B).
The command driver circuit 28-8 is a ×3 circuit (i.e., includes three copies of the elements illustrated within the dotted box), with each circuit including a flip-flop having a true output and an output buffer/driver that generates a corresponding command. The three flip-flops are configured to receive a back side row address strobe input signal (ras), a back side column address strobe input signal (cas) and a back side write enable input signal (we), respectively. The generated commands include an active low row address strobe signal RAS#B, an active low column address strobe signal CAS#B and an active low write enable signal WE#B for the back side of the DIMM 30. The phase interpolator, which is responsive to the timing signals and a command skew control signal (rascaswe_ctl) for the back side, sets the skew associated with all three commands (RAS#B, CAS#B and WE#B).
The command driver circuit 28-9 is a ×4 circuit (i.e., includes four copies of the elements illustrated within the dotted box), with each circuit including a flip-flop having a true output and an output buffer/driver that generates a corresponding command. The four flip-flops are configured to receive a pair of chip select signals and a pair of clock enable signals for the back side (cs and cke, which correspond to cs[1:0]#B and cke[1:0]B). The phase interpolator, which is responsive to the timing signals and a command skew control signal (cscke_ctl) for the back side, sets the skew associated with all four commands (CS[1:0]#B and CKE[1:0]B).
The back on-die termination (ODTB) driver circuit 28-10 includes a flip-flop having a true output and an output buffer/driver that generates a corresponding on-die termination signal (ODTB) for the back side of the DIMM 30. The flip-flop is configured to receive an on-die termination signal (odt) for the back side. The phase interpolator, which is responsive to the timing signals and an ODT skew control signal (odt_ctl) for the back side, sets the skew associated the back on-die termination signal (ODTB).
The data and strobe DDR driver circuit 28-11 is a ×18 circuit that is configured to receive 144 bits of output data dout[143:0] on 72 data lines operating at dual data rates and generate data and check bits CB[7:0] and DQ[63:0] on eighteen groups of four data output lines. Each of the eighteen DDR driver circuits contains a respective ×4 bidirectional data driver circuit therein that is responsive to both rising and falling edges of a synchronizing signal generated by a respective phase interpolator (PI), which is responsive to a respective data out skew control signal (dout_ctl). The eighteen data out skew control signals dout_ctl[8:0] support independent skew control for eighteen groups of four output data lines. As illustrated, the ×4 bidirectional data driver circuit includes flip-flops and an output buffer in the output path and an input buffer and flip-flops in the input path. The output buffer is responsive to an output enable signal (OE), which supports a high impedance output state. This output buffer also supports slew rate and output impedance control as illustrated by FIG. 2C.
The data and strobe DDR driver circuit 28-11 is also configured to generate 18 pairs of data strobe signals (DQS[17:0] and DQS[17:0]#) when the DRAM interface circuit 26 is writing data to the DRAMs 22_1 to 22_7 and receive data strobe signals when reading and capturing data read from the DRAMs 22_1 to 22_7. The data strobe signal lines are driven by eighteen pairs of output buffers that are responsive to an output enable signal (OE). Like the output buffer in the ×4 bidirectional data driver circuit, each pair of output buffers supports slew rate and output impedance control as illustrated by FIG. 2C. The timing of each pair of data strobe signal lines (DQS and DQS#) is controlled by a respective phase interpolator (PI). Each of the eighteen phase comparators is responsive to a respective one of the eighteen data strobe skew control signals dqs_ctl[8:0].
The control of timing to the data receiving portion of the ×4 bidirectional data driver circuit also supports eighteen independent offsets in the capture of read data (din[143:0]). These offsets are controlled by the eighteen 9-bit offset control signals offset_ctl[8:0], which are provided to a DLL finite state machine (FSM). This DLL FSM generates outputs that are provided to the eighteen phase interpolators associated with the ×4 bidirectional data driver circuits and the eighteen phase interpolators associated with the incoming strobe signals (DQS[17:0], DQS[17:0]#) received from the DRAMs 22_1 to 22_7.